The present invention relates to a method of programming a NAND multi-level cell flash memory device, and more particularly to a method of programming that reduces the interference between cells.
A semiconductor memory device is generally divided into a volatile memory device and a non-volatile memory device. In the volatile memory device, data is erased when the supply of power is stopped. In the non-volatile memory device, data is maintained even though the supply of power is stopped.
Recently, the non-volatile flash memory device has become widely used. The two main types of flash memory device is a NOR flash memory and a NAND flash memory. The NOR flash memory has excellent random access time characteristics because memory cells are independently connected to bit lines and word lines. Whereas, in the NAND flash memory, only one contact is required for one cell string because memory cells are connected in series, and so the NAND flash memory has excellent characteristics for integration. Recently, the demand for high density flash memory has increased, and thus the NAND flash memory having high degree of integration has been widely employed as the flash memory device of choice.
A single level cell (hereinafter, referred to as “SLC”) is employed when storing 1 bit data in a memory cell. A multi-level cell (hereinafter, referred to as “MLC”) is employed for storing data of 2 bits or more in a memory cell. Recently, because of the need for a flash memory device having a high degree of integration, the MLC has been actively studied.
The MLC generally has at least four threshold voltage levels, and also has four or more data storing conditions corresponding to the threshold voltage levels.
A typical MLC has four data storing conditions, e.g. ‘11’, ‘10’, ‘00’ and ‘01’. Here, when the four data storing conditions corresponds to one of the threshold voltage levels, a 2 bit data can be stored in a memory cell.
The MLC is programmed by a Fowler-Nordheim tunneling phenomenon. A program voltage is applied to a row of gates of a selected cell, and a ground voltage Vss is provided to the channels of the selected cell. Accordingly, a high electric field is formed between a floating gate of a programmed cell and a channel.
FIG. 1 is a view illustrating a method of programming a common flash memory device. The MLC stores data of 2 bits or more, wherein the bits are divided into a most significant bit (hereinafter, referred to as “MSB”), and a least significant bit (hereinafter, referred to as “LSB”). For example, when storing the binary value ‘10’, the MSB and LSB are 1 and 0, respectively.
Accordingly, in case that LSB is programmed in ‘11’, data storing condition ‘11’ is converted into data storing condition ‘10. Subsequently, to program MSB, the programming result of LSB is detected, and then the MSB is programmed in accordance with the detecting result.
For instance, if LSB is detected to be 1, data storing condition is ‘11’. Accordingly, in case of programming the MSB, data storing condition becomes ‘01’. If, on the other hand, LSB is detected to be 0, data storing condition is ‘10’. Accordingly, in case of programming the MSB, data storing condition becomes ‘00’.
However, since the MLC has more threshold voltage levels than the SLC (i.e., four instead of two), the read margin between the threshold voltage states for the MLC becomes more important.
Generally, the factors for causing interference between adjacent cells and changing the threshold voltage occurs commonly in NAND flash memory. The change in the threshold voltage increases as the flash memory devices become highly integrated and the density increases. The device characteristics of the flash memory are deteriorated.
In addition, comparing A of FIG. 2B to A of FIG. 2A, the threshold voltage distribution of the cell is increased due to the interference, and thus a pass voltage Vpass in FIG. 2B needs to be increased so that the cells have the same read margins as shown in B and C of FIGS. 2A and 2B. However, read disturb will occur due to the increase of the pass voltage Vpass.
In one embodiment, a method of programming a NAND flash memory device includes providing a flash memory device where N word lines are disposed between a drain selecting line and a source selecting line, each word line being assigned with a first bit line and a second bit line; performing an LSB program operation for storing a lower rank data bit from a first word line adjacent to the source selecting line to an Nth word line adjacent to the drain selecting line; and performing a MSB program operation for storing a higher rank data bit from the first word line adjacent to the source selecting line to the Nth word line adjacent to the drain selecting line. The LSB program operation includes: selecting a given word line, and programming first memory cells coupled to the first bit line of the selected word line and then second memory cells coupled to the second bit line of the select word line, wherein the selecting-a-given-word-line step and the programming-first-memory-cells step are repeated until the Nth word line has been processed. The first bit line is an even bit line, and the second bit line is an odd bit line.
In one embodiment, the MSB program operation includes selecting a given word line, and programming first memory cells coupled to the first bit line of the selected word line and then second memory cells coupled to the second bit line of the select word line, wherein the selecting-a-given-word-line step and the programming-first-memory-cells step are repeated until the Nth word line has been processed. The LSB program operation uses a method of incrementally increasing a word line voltage that is smaller than a word line voltage used for the MSB program operation.
In another embodiment, a method of programming a NAND flash memory device includes providing a flash memory device, wherein word lines are disposed between a drain selecting line and a source selecting line, wherein a first word line is provided adjacent to the source selecting line and a last word line is provided adjacent to the drain selecting line; and selecting a word line to program memory cells coupled to the selected word line to perform an even LSB program operation and an odd LSB program operation for the selected first word line. Each of the word lines is selected until all of the word lines have been selected, so that the even LSB program operation and the odd LSB program operation can be performed for all of the word lines. The even LSB program operation is performed to store a lower rank data bit in memory cells coupled to an even bit line assigned a selected word line. The odd LSB program operation is performed to store a lower rank data bit in memory cells coupled to an odd bit line assigned to the selected word line.
In another embodiment, the word lines are selected sequentially from the first word line until the last word line has been selected. The method further includes performing an even MSB program operation for storing a higher rank data bit in the memory cells coupled to the even bit line of the selected word line; and performing an odd MSB program operation for storing a higher rank data bit in memory cells coupled to the odd bit line of the selected word line, wherein the even MSB program operation and the odd MSB program operation are performed for each selected word line until the even MSB program operation and the odd MSB program operation have been performed for all of the selected word lines. The LSB program operation uses a method of incrementally increasing a word line voltage that is smaller than a word line voltage used for the MSB program operation.